High-speed AC-coupled serial link channels delivering an effective transmission rate above 5 Gigabits per second (Gbps) in a backplane environment are subject to significant signaling challenges. For example, inter-symbol interference (ISI) may be introduced due to a significant DC component in a transmitted data stream. Attenuation caused by conductor and dielectric losses also causes dispersion ISI. Another important ISI component is reflections, which are essentially multipath components of a signal and originate from impedance discontinuities such as those caused by connectors of line cards at both transmit and receive ends. In addition to ISI distortion, cross-talk effects from far and near end adjacent channels is becoming increasingly significant in high-speed serial link channels.
Transmitters and receivers are required to compensate for most signal distortion using very low complexity schemes in order to obtain a target bit error rate (BER) of less than or equal to 10−17 at Gbps rates and under severe power and complexity restrictions. This constrained space presents significant challenges to well-known signal processing techniques, and sub-optimal but efficient alternatives are sometimes needed to fulfill the task.
For example, to counteract DC balance and channel attenuation at high bit rates, coding schemes are often employed. Specifically, coding schemes may improve transmission characteristics by reducing ISI, providing improved DC balancing properties, provide transitions for use by receivers, and providing improved BER through error detection and correction. In addition, coding schemes may also provide framing (i.e., byte boundaries), as well as provide protocol support through the use of control characters.
The most popular coding scheme, which is used primarily in non-return to zero (NRZ) signaling systems, is an 8-bit/10-bit (8b/10b) coding scheme. In the 8b/10b coding scheme, an 8-bit byte is coded into a 10-bit byte, resulting in an overhead of 25%. As transmission rates scale to more than 5 Gbps, the need for bandwidth saving techniques in coding become necessary. This is even more imperative for bandwidth limited channels.
A committee of the Institute for Electrical and Electronic Engineers (IEEE) working on standardizing 10G Ethernet has established a 64-bit/66-bit (64b/66b) coding scheme. In accordance with the IEEE 64b/66b standard, a 64-bit payload block is coded into a 66-bit payload/synchronization block, resulting in an overhead of 3.125%. The extra two bits in the 66-bit payload/synchronization block are synchronization bits for indicating whether the remaining 64 bits in the 66-bit payload/synchronization block contain control bits, as shown in FIG. 1. The two synchronization bits in the IEEE 64b/66b  standard also guarantee that at least one transition is present in every 66-bit payload/synchronization block. The IEEE 64b/66b standard is also beneficial in that it allows 10 Gigabits (Gb) of real data to be transmitted at 10.3125 Gbps.
However, the IEEE 64b/66b standard is deficient in several regards. For example, the IEEE 64b/66b standard does not provide for DC guaranteed balancing, which is necessary so that the common mode voltage at a receiver remains bounded within known values. Without DC balancing, receiver sensitivity is compromised. Also, while the IEEE 64b/66b standard supports NRZ and 2-level pulse amplitude modulation (2-PAM) signaling schemes, it does not support 4-PAM or multi-PAM signaling schemes, which allow for significant increases in bandwidth. Furthermore, the IEEE 64b/66b standard does not address error detection, which is a crucial parameter in many systems. Additionally, the IEEE 64b/66b standard guarantees only one transition in every 66-bit payload/synchronization block, which is often insufficient for clock recovery operations.
In view of the foregoing, it would be desirable to provide a low overhead coding technique which overcomes the above-described inadequacies and shortcomings of the IEEE 64b/66b standard and other coding schemes.